The invention relates to an arrangement for time division multiplex data transmission with a bus system which includes a bus line and a plurality of participators connected to the bus line which are in data transmitting connection with each other in a predetermined succession in a predetermined combination, in which preferably each participator has at least one progammable counter, the counting input of which is connected with a synchronizing signal generator and the output of which is connected with switching means to produce a data transmitting connection between the bus line and a data source or sink of this participator, whereby the counters of all participators are synchronized with each other according to Patent application No. P 27 50 818.5-31.
In known series bus systems, data can be transmitted in a predetermined order between respective given participators on a bus line, which can include a data conductor and an energy source. Even if all participators connected to the bus conductor are always ready to respond, only one participator or a certain group of participators can receive the respectively transmitted data for further processing.
To select this participator or a certain group of participators, according to the prior art an address signal is transmitted which only allows the desired other participators or desired other group of participators to transmit the information for further processing in this participator. The end of this transmission is indicated by an end signal on the bus line, which causes the next participator or group of participators to send their information with preceeding address signal and subsequent end signal. This type of known arrangement for series or time division multiplex data transmission can be built to transmit analog signals and/or so-called discrete signals, which only contain yes/no information.
In this type of bus system, in order to improve the relative time period in which the bus system is available for transmitting actual useful information in relation to the total time period of the transmission, which includes the transmission of the address signals and end signals, according to Patent application No. P 27 50 818.5-31 it has already been proposed that each participator have at least one programmable counter which gives a control signal at a programmed number and which is reset to zero after reaching a predetermined counting capacity, which is the same for all counters; that a counting input of the counter is connected with a synchronizing signal generator; that a first control output of the counter is connected with switching means for producing the data transmitting connection between the bus line and a data source or sink of this participant; and that the counters of all participators are synchronized with each other.
According to the above mentioned patent, a measure is also taken so that even during a short circuit in one or more transmitting output stages of the participator there is sufficient signal deviation or swing on the bus conductor, which can be evaluated by the participators operating as receivers. For this purpose, the transmitting output stages of the participator are connected to the bus line by means of resistors.
According to this arrangement, however, the bus system is only protected against breakdown in special cases of short circuits, namely short circuits in the transmitting output stages.